In conventional CMOS circuits the input signal swing is equal to the supply voltage. With an input signal swing equal to the supply voltage the static current in the CMOS circuit is only attributed to device leakage current as one of the device is always OFF.
There are also situations where analogue signals are received that have a voltage swing less than the supply voltage. As an example, such a signal may be a low-level clock signal which occurs at the low-speed clock input to which a crystal is connected. This low-level clock signal has to be converted into a digital clock signal. In this application the input low-level clock signal has a voltage swing which is less than the supply voltage. This will lead to a static current in the input stage connected to the clock input when the input signal is in a high logic state which has a level lower than the supply voltage (VDD). Then the pull-down transistor (NMOST) is “ON” and pull-up transistor (PMOST) is not completely “OFF”. The resulting static current (that runs through both transistors) is detrimental for low power applications. Solutions to this problem, namely to find a receiver circuit which does not suffer from static leakage current in steady state conditions, have been reported in the prior art.
For example, U.S. Pat. No. 6,225,838B1 discloses an integrated circuit buffer including an inverter and a circuit that selectively powers the inverter at a first potential (e.g., VDDL-alpha) when the output of the inverter is at a first logic level (e.g., logic “0”), and at a second higher potential (e.g., VDDL) when the output of the inverter is at a second logic level (e.g., logic “1”) opposite the first logic level. The integrated circuit buffer may include an inverter configured as a PMOS pull-up transistor having a gate electrode electrically coupled to an input node and a drain electrode electrically coupled to an output node, and an NMOS pull-down transistor having a gate electrode electrically coupled to the input node and a drain electrode electrically coupled to the output node. A diode and switch are also provided to perform the selective powering operation. The diode is provided to reduce the magnitude of the power supply voltage which the inverter receives when the PMOS pull-up transistor is inactive (thereby reducing the static leakage current) and the switch is provided to bypass the diode when PMOS pull-up transistor is active.
Similar CMOS input circuits have been disclosed in many other documents, e.g. DE19719448, U.S. Pat. No. 5,378,943, EP0595318A2, and U.S. Pat. No. 7,119,578B2. In any case all these documents rely on the short-circuiting of a diode-connected transistor in a supply path under certain states of the output voltage.
In view of the above it may be desired to find an alternative solution.